12th Int'l Symposium on Quality Electronic Design

In this paper we review some of the state of the art techniques for parasitic interconnect extraction in the presence of random geometrical variations due to uncertainties in the manufacturing processes. We summarize some of the most recent development in both sampling based (non-intrusive) and expansion based (intrusive) algorithms for the extraction of both general impedance and capacitance in the presence of random geometrical variations. In particular, for non-intrusive algorithms we discuss both the stochastic model reduction algorithm for general impedance extraction under uncertainty and the path recycling floating random walk algorithm for capacitance extraction under uncertainty. For intrusive algorithms we summarize the Neumann expansion, the standard stochastic Galerkin method, the combined Neumann Hermite expansion and the stochastic dominant singular vectors method. Finally, we end the paper by comparing the presented algorithms on four very large and complex impedance and capacitance extraction examples.